This paper presents a hardware implementation of CDF(2,2) wavelet image compressor. The design demonstrates that high quality circuit implementation is possible through the use of suitable data organization (partitioned approach) and algorithm-to-architecture mappings ( More
This paper presents a hardware implementation of CDF(2,2) wavelet image compressor. The design demonstrates that high quality circuit implementation is possible through the use of suitable data organization (partitioned approach) and algorithm-to-architecture mappings (parallel-ism or pipelining). A VHDL code for CDF(2,2) was developed to satisfy our objective. Then it was synthesized in Foundation 5.1 software and downloaded to CPLD XC9572 by a JTAG ByteBlaster cable. The original image was transmitted through serial port. The AVR’s ATmega8535 was used to implement serial protocol to and back from the CPLD. The main goal is to reach a higher performance and throughput with a single CPLD. Details of the encoder design have been discussed and the results are presented.
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